Replication of Space-Shuttle Computers in FPGAs and ASICs

A document discusses the replication of the functionality of the onboard space-shuttle general-purpose computers (GPCs) in field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs). The purpose of the replication effort is to enable utilization of proven space-shuttle flight software and software-development facilities to the extent possible during development of software for flight computers for a new generation of launch vehicles derived from the space shuttles. The replication involves specifying the instruction set of the central processing unit and the input/output processor (IOP) of the space-shuttle GPC in a hardware description language (HDL). The HDL is synthesized to form a "core" processor in an FPGA or, less preferably, in an ASIC. The core processor can be used to create a flight-control card to be inserted into a new avionics computer. The IOP of the GPC as implemented in the core processor could be designed to support data-bus protocols other than that of a multiplexer interface adapter (MIA) used in the space shuttle. Hence, a computer containing the core processor could be tailored to communicate via the space-shuttle GPC bus and/or one or more other buses

Use of Field Programmable Gate Array Technology in Future Space Avionics

Fulfilling NASA's new vision for space exploration requires the development of sustainable, flexible and fault tolerant spacecraft control systems. The traditional development paradigm consists of the purchase or fabrication of hardware boards with fixed processor and/or Digital Signal Processing (DSP) components interconnected via a standardized bus system. This is followed by the purchase and/or development of software. This paradigm has several disadvantages for the development of systems to support NASA's new vision. Building a system to be fault tolerant increases the complexity and decreases the performance of included software. Standard bus design and conventional implementation produces natural bottlenecks. Configuring hardware components in systems containing common processors and DSPs is difficult initially and expensive or impossible to change later. The existence of Hardware Description Languages (HDLs), the recent increase in performance, density and radiation tolerance of Field Programmable Gate Arrays (FPGAs), and Intellectual Property (IP) Cores provides the technology for reprogrammable Systems on a Chip (SOC). This technology supports a paradigm better suited for NASA's vision. Hardware and software production are melded for more effective development; they can both evolve together over time. Designers incorporating this technology into future avionics can benefit from its flexibility. Systems can be designed with improved fault isolation and tolerance using hardware instead of software. Also, these designs can be protected from obsolescence problems where maintenance is compromised via component and vendor availability.To investigate the flexibility of this technology, the core of the Central Processing Unit and Input/Output Processor of the Space Shuttle AP101S Computer were prototyped in Verilog HDL and synthesized into an Altera Stratix FPGA

Case Study of the Space Shuttle Cockpit Avionics Upgrade Software

The purpose of the Space Shuttle Cockpit Avionics Upgrade project was to reduce crew workload and improve situational awareness. The upgrade was to augment the Shuttle avionics system with new hardware and software. An early version of this system was used to gather human factor statistics in the Space Shuttle Motion Simulator of the Johnson Space Center for one month by multiple teams of astronauts. The results were compiled by NASA Ames Research Center and it was was determined that the system provided a better than expected increase in situational awareness and reduction in crew workload. Even with all of the benefits nf the system, NASA cancelled the project towards the end of the development cycle. A major success of this project was the validation of the hardware architecture and software design. This was significant because the project incorporated new technology and approaches for the development of human rated space software. This paper serves as a case study to document knowledge gained and techniques that can be applied for future space avionics development efforts. The major technological advances were the use of reflective memory concepts for data acquisition and the incorporation of Commercial off the Shelf (COTS) products in a human rated space avionics system. The infused COTS products included a real time operating system, a resident linker and loader, a display generation tool set, and a network data manager. Some of the successful design concepts were the engineering of identical outputs in multiple avionics boxes using an event driven approach and inter-computer communication, a reconfigurable data acquisition engine, the use of a dynamic bus bandwidth allocation algorithm. Other significant experiences captured were the use of prototyping to reduce risk, and the correct balance between Object Oriented and Functional based programming

System Software Framework for System of Systems Avionics

Project Constellation implements NASA's vision for space exploration to expand human presence in our solar system. The engineering focus of this project is developing a system of systems architecture. This architecture allows for the incremental development of the overall program. Systems can be built and connected in a "Lego style" manner to generate configurations supporting various mission objectives. The development of the avionics or control systems of such a massive project will result in concurrent engineering. Also, each system will have software and the need to communicate with other (possibly heterogeneous) systems. Fortunately, this design problem has already been solved during the creation and evolution of systems such as the Internet and the Department of Defense's successful effort to standardize distributed simulation (now IEEE 1516). The solution relies on the use of a standard layered software framework and a communication protocol. A standard framework and communication protocol is suggested for the development and maintenance of Project Constellation systems. The ARINC 653 standard is a great start for such a common software framework. This paper proposes a common system software framework that uses the Real Time Publish/Subscribe protocol for framework-to-framework communication to extend ARINC 653. It is highly recommended that such a framework be established before development. This is important for the success of concurrent engineering. The framework provides an infrastructure for general system services and is designed for flexibility to support a spiral development effort

Neuromotor tolerability and behavioural characterisation of cannabidiolic acid, a phytocannabinoid with therapeutic potential for anticipatory nausea

Rationale: Anticipatory nausea (AN) is a poorly controlled side-effect experienced by chemotherapy patients. Currently, pharmacotherapy is restricted to benzodiazepine anxiolytics, which have limited efficacy, significant sedative effects, and induce dependency. The non-psychoactive phytocannabinoid, cannabidiolic acid (CBDA), has shown considerable efficacy in pre-clinical AN models, however determination of its neuromotor tolerability profile is crucial to justify clinical investigation. Provisional evidence for appetite-stimulating properties also requires detailed investigation. Objectives: To assess the tolerability of CBDA in locomotor activity, motor coordination and muscular strength tests, and additionally for ability to modulate feeding behaviours. Methods: Male Lister hooded rats administered CBDA (0.05-5 mg/kg; p.o.) were assessed in habituated open field (for locomotor activity), static beam and grip strength tests. A further study investigated whether these CBDA doses modulated normal feeding behaviour. Finally, evidence of anxiolytic-like effects in the habituated open field prompted testing of 5 mg/kg CBDA for anxiolytic-like activity in unhabituated open field, light/dark box and novelty-supressed feeding (NSF) tests. Results: CBDA had no adverse effects upon performance in any neuromotor tolerability test, however anxiolytic-like behaviour was observed in the habituated open field. Normal feeding behaviours were unaffected by any dose. CBDA (5 mg/kg) abolished the increased feeding latency in the NSF test induced by the 5-HT1AR antagonist, WAY-100,635, indicative of anxiolytic-like effects, but had no effect on anxiety-like behaviour in the novel open field or light/dark box. Conclusions: CBDA is very well tolerated and devoid of the sedative side-effect profile of benzodiazepines, justifying its clinical investigation as a novel AN treatment

Case Study of Using High Performance Commercial Processors in a Space Environment

The purpose of the Space Shuttle Cockpit Avionics Upgrade project was to reduce crew workload and improve situational awareness. The upgrade was to augment the Shuttle avionics system with new hardware and software. A major success of this project was the validation of the hardware architecture and software design. This was significant because the project incorporated new technology and approaches for the development of human rated space software. An early version of this system was tested at the Johnson Space Center for one month by teams of astronauts. The results were positive, but NASA eventually cancelled the project towards the end of the development cycle. The goal to reduce crew workload and improve situational awareness resulted in the need for high performance Central Processing Units (CPUs). The choice of CPU selected was the PowerPC family, which is a reduced instruction set computer (RISC) known for its high performance. However, the requirement for radiation tolerance resulted in the reevaluation of the selected family member of the PowerPC line. Radiation testing revealed that the original selected processor (PowerPC 7400) was too soft to meet mission objectives and an effort was established to perform trade studies and performance testing to determine a feasible candidate. At that time, the PowerPC RAD750s where radiation tolerant, but did not meet the required performance needs of the project. Thus, the final solution was to select the PowerPC 7455. This processor did not have a radiation tolerant version, but faired better than the 7400 in the ability to detect failures. However, its cache tags did not provide parity and thus the project incorporated a software strategy to detect radiation failures. The strategy was to incorporate dual paths for software generating commands to the legacy Space Shuttle avionics to prevent failures due to the softness of the upgraded avionics

Isolating Chromosomes of the Komodo Dragon: New Tools for Comparative Mapping and Sequence Assembly.

We developed new tools to build a high-quality chromosomal map of the Komodo dragon (Varanus komodoensis) available for cross-species phylogenomic analyses. First, we isolated chromosomes by flow sorting and determined the chromosome content of each flow karyotype peak by FISH. We then isolated additional Komodo dragon chromosomes by microdissection and amplified chromosome-specific DNA pools. The chromosome-specific DNA pools can be sequenced, assembled, and mapped by next-generation sequencing technology. The chromosome-specific paint probes can be used to investigate karyotype evolution through cross-species chromosome painting. Overall, the set of chromosome-specific DNA pools of V. komodoensis provides new tools for detailed phylogenomic analyses of Varanidae and squamates in general.non